Microprocessors often contain a small dedicated memory, commonly referred to as a control read only memory (CROM), for storing micro-code instructions. An array of bitlines and wordlines are used to access the micro-code stored in the CROM. As microprocessors became faster, there arose a need to access the CROM more quickly. One solution involved precharging the bitlines to a level close to the trip point of the sensing stage. Thereby, a small swing in voltage on the bitlines would cause the bitline to trigger a sense amplifier and decoder. One implementation involved the coupling of an N-channel pull-up transistor to a bitline to set the precharge level. Consequently, the bitline would be precharged to the supply voltage minus the threshold voltage of the N-channel transistor. For example, given a supply voltage of V.sub.CC =3.3 v, an N-channel threshold of V.sub.TN =1.0 v and a trip point of V.sub.TP =1.6 v, bitline voltage V.sub.CC -V.sub.TN =3.3 v-1.0 v= 1.0 v=2.3 v would only have to be dropped by approximately 2.3 v-V.sub.TP =0.7 v. Hence, by precharging the bitline to 1 V.sub.TN down from V.sub.CC, the CROM can be accessed faster because a 0.7 v drop can be achieved much more quickly than a 1.7 v drop. Often the speed of the sensing stage is reliant on this initial precharge level. If a mechanism is present that causes a bitline to reach a level greater than V.sub.CC -V.sub.TN prior to being accessed, then the access time of the sensing circuit is degraded. CROM sensing circuits using such a V.sub.TN precharge level incur a push-out from wordline active to valid output when a bitline is at full V.sub.CC level when the access begins. In some cases this push-out can be as high as 50%. This push-out behavior is typical of such "level dependent" sensing circuits that are used to reach the access times demanded by the high clock frequencies of today's microprocessors.
There are several situations where a ROM bitline reliant on N-channel precharging would reach levels greater than V.sub.CC minus V.sub.TN. It is known that the sub-threshold leakage of an N-channel pull-up, precharging a typical CROM bitline will be orders of magnitude greater than the junction leakage of a single programming diffusion. In addition, the downward leakage through the programming device is minimal compared to the upward leakage through the pull-up because the gate to source potential of an off programming device is very near zero. Conversely, the pull-up's gate to source potential varies with the bitline level. Thus, its sub-threshold leakage is initially relatively high and falls off exponentially only as the bitline (e.g., the source) leaks up. The net leakage on the bitline causes it to drift upwards toward the chip supply level.
In addition, a ROM is sensitive to the effects of subthreshold leakage when utilizing N-channel bitline precharge. This is particularly true if a stop-clock feature is implemented. During stop-clock, the CROM bitlines might rest indefinitely in the precharge state. Consequently, there is ample time for the bitlines to leak to the chip supply level. Hence, traditional solutions that relied on nominal activity factors to discharge the bitlines periodically no longer apply to stop-clock microprocessors.
In addition to static leakage mechanisms, the bitlines of a ROM are susceptible to coupling from neighboring array structures. Furthermore, the bitlines are also susceptible to any overlying signal lines present in a multi-level metal process. The disturbance from such coupling sources is aggravated by the variable loading of ROM bitlines (minimally programmed bitlines are lightly loaded and their voltage levels can be moved easier). Using an N-channel bitline precharge structure such bitlines can be coupled towards the supply level or even higher. As a result, they are typically not recoverable to their desired precharge level.
In summary, prior art CROM array bitline levels are typically sensitive to leakage and coupling disturbance if N-channel precharge architecture were to be used. Such disturbance results in performance or functionality problems if "normal" precharge levels are designed as an integral part of the sensing scheme. Implementing a stop-clock mode aggravates this problem since it might create lengthy periods of leakage opportunity. These problems apply to any ROM or RAM array structure where the bitline precharge function is performed by devices that enter cut off mode as the bitline precharge level is reached (e.g., an N-channel pull-up sourced to the chip supply) and where the initial bitline precharge level is a critical consideration for sensing. The leakage issues would also be extendible to any generic CMOS enhancement device process, since they rely on fundamental device sub-threshold and junction behaviors.